Data communications can be performed using a serializer/deserializer (SerDes), which typically includes a pair of functional blocks that convert between serial data and parallel data. The SerDes can be implemented in an integrated circuit transceiver, such as on a SerDes link between two pins on a board.
FIG. 1A illustrates a known SerDes communication link including a SerDes transmitter 10, a channel 20, a SerDes receiver 30, receiver logic 40 and forward error correction (FEC) module 42. The SerDes transmitter 10 includes a Parallel In Serial Out (PISO) converter 12. Since the clock frequencies used within an integrated device are much slower than the transmission rate on a serial line, the input to the transmitter 10 is a parallel set of values that are serially shifted out of the PISO converter 12 to create a high speed serial stream. The SerDes transmitter 10 optionally includes a transmit (TX) filter 14 configured to combat inter-symbol interference (ISI) occurring in the channel 20. A simple TX filter 14 is often used, such as a 3-tap finite impulse response (FIR) filter. In some implementations, the channel 20 physically comprises bond wires, package pins and physical board traces or cables, each of which can introduce ISI that must be compensated for within the overall system.
The SerDes receiver 30 includes one or more samplers 32. Prior to sampling, a receiver (RX) filter 34 can be provided to remove as much ISI as possible through standard filtering operations. In implementations in which the channel is a low-pass channel, the RX filter 34 implements a high-pass function often implemented as a FFE (Feed-Forward Equalizer) or a CTLE (Continuous Time Linear Equalizer). The sampler(s) 32 convert the received signal back into a serial stream of 1s and 0s. A Decision Feedback Equalizer (DFE) 36 uses previously decided bits and decisions on past samples to further equalize the channel, often by multiplying up the number of physical samplers within a system or changing where the samplers are located. A Serial In Parallel Out (SIPO) converter 38 converts the high-speed received stream of 1s and 0s back to a lower frequency parallel interface. Note while line rates of SerDes can be 25 GHz, 56 GHz or even 112 GHz, chip-internal clocks tend to be in the range 500 MHz to 1.5 GHz.
FIG. 1B illustrates a simplified view of SerDes receiver 30 and receiver logic 40. The SerDes receiver 30 includes one or more data samplers 32. A DC input is provided within the SerDes receiver 30 for offline calibration of the one or more data samplers 32. The receiver logic 40 receives and operates on the raw bits from the SerDes receiver 30. The receiver logic 40 can have similar or higher complexity than the SerDes receiver 30, and often includes its own micro-processor to help offload some of the tasks.
Historically, a SerDes link with 1e-15 or 1e-12 error rate has not included forward error correction (FEC). As channel speeds increase, ISI also increases, forcing larger and more complex receiver designs that now require a FEC to be included in order to achieve bit error rate requirements. Many faster SerDes links now include FEC, such as FEC 42 in FIG. 1B, which can be provided as part of the receiver logic 40. The receiver logic 40 can identify FEC boundaries, extract FEC blocks from the input data stream, and pass these blocks through the FEC module 42.
Offset calibration (OsCal) is desirable to ensure accurate operation and to compensate for “drift”. Consider FIG. 2, which illustrates a simplified eye diagram for a normal sampler, such as a data sampler 32. The received analog waveform exists somewhere in the area between the inner eye boundary 50 and the outer eye boundary 52, and most often goes half way between these boundaries, either in the upper eye 56 or in the lower eye 58. A sampler, such as data sampler 32, has a sampling level, or location, 54 that is ideally sitting at the middle of the upper inner eye boundary and the lower inner eye boundary, nominally 0V DC. Any analog signal above the sampling level is taken to be a 1 while anything below the sampling level is taken to be a 0. In doing so, a sampler such as the data sampler 32 converts an analog waveform into a digital value using the sampling level.
FIG. 3 illustrates an eye diagram for a sampler, such as the data sampler 32, where the sampling level exhibits an offset. In FIG. 3, the sampling level has drifted up, unintentionally and perhaps due to voltage or temperature (VT) drift, to be within the upper eye 56, as shown by offset high sampling level 64. For example, what was presumed to have been ground may have moved up from 0 mV to 10 mV. In such a situation, the sampler 32 will sometimes convert a signal in the upper eye to be a 0 (when the signal is below the offset sampling level 64) and thereby make a 1->0 bit-flip, which requires correction. With a sampler offset in the upper eye, the sampler will make many 1->0 flips, and will make almost no 0->1 flips. Moving the offset sampling level 64 down will eventually bring the level below the upper inner eye boundary 50 and significantly reduce the bit-error rate.
Offset calibration is typically performed before a device is put into service. A known off-line OsCal method is to set the input to a sampler to 0V DC and then allow the sampler to collect digital samples. If the sampling level is truly 0V DC, then random noise will cause the sampler to generate 50% ones and 50% zeroes. If, for example, the actual sampling level is higher than 0V then the sampled values will be biased towards 0s. If, for example, the actual sampling level is lower than 0V then the sampled values will be biased towards 1s. Given this outcome, the OsCal method can determine that the sampling level is to be decreased, or increased, respectively. OsCal can be repeated later, to determine whether further calibration is needed, but repeating this procedure requires taking the sampler out of service during the repeated OsCal.
FIG. 4 illustrates a known dual SerDes receiver. In the SerDes receiver of FIG. 4, two completely separate SerDes receivers 30-1 and 30-2 are provided in parallel, to facilitate being able to perform the OsCal method and still process data. With two receivers available, in a first state as shown in FIG. 4 a first receiver 30-1 is processing the live traffic while a second receiver 30-2 is taken off-line allowing the OsCal method to be run on all the data samplers 32-2. In this first state, switches 31 and 33 are in respective first positions. In a second state (not shown, but with the switches 31 and 33 in FIG. 4 being in opposite positions), the second receiver 30-2 is processing the live traffic, and the first receiver 30-1 is taken off-line allowing the OsCal method to be run on all the data samplers 32-1. These two parallel receivers take up a lot of physical area, sometimes double the area for many components. Each SerDes receiver 30-1 and 30-2 is performing offset calibration while the other is processing live data traffic, and the receivers regularly switch operations, possibly alternating every few seconds.
When a SerDes receiver is in service, the device is in open loop. When entering open loop, the thermal environment may not yet have reached equilibrium or full operating conditions, i.e. the voltage/temperature (VT) situation may not yet have stabilized. There are also variations in power requirements as circuitry in the overall system reaches full operating conditions; such changes in power requirements lead to different output voltages, which can contribute to VT drift. There can be a significant difference, or delta, between the thermal and power environments during operation as compared to the pre-service environment.
Improvements in drift compensation approaches are desirable.